Prashant
Mishra
Hardware Engineer & ML Researcher
Building high-performance digital systems, VLSI circuits, and intelligent networks at the intersection of silicon and software.
Graduate researcher blending hardware design, signal processing, and machine learning.
M.Tech — Electronics & Signal Processing
IIT Indore · Roll No. 2502102014
CGPA 8.8 / 10GATE 2025 — Electronics & Communication
All India Rank: 1297
Top PercentileI'm a graduate student at IIT Indore majoring in Electronics, passionate about Digital Systems, CPU Architecture, VLSI Design and Signal Processing, building efficient and high-performance hardware systems. Skilled in AI Algorithms and ML models.
My thesis explores LLM-driven network slicing using the RAN Intelligent Controller (RIC), sitting at the fascinating boundary between AI and next-gen wireless infrastructure. I also hold an IEEE publication on zero-day attack detection.
Previously, I completed a research internship at IIT Kanpur under Prof. Abhilash Patel, working on neural modeling of genetic circuits using reinforcement learning and neural ODEs.
Hardware, AI, and wireless systems — from silicon to software.
RISC-V Pipelined Processor Implementation
A full 5-stage pipelined RISC-V processor supporting the RV32I ISA. Implements hazard detection, forwarding unit, branch prediction, and complete decode/execute/memory/writeback pipeline. Written in Verilog with testbench verification.
Intelligent RAN slicing using Large Language Models and xApps on the O-RAN RIC framework for autonomous 5G resource management.
ML-based intrusion detection system for zero-day attacks in network traffic using ensemble classifiers and anomaly detection.
End-to-end ASR pipeline using LSTM networks with beam search decoding, achieving low word-error rates on benchmark datasets.
From RTL design to ML inference pipelines.