Back to Home

About Me

Hardware engineer, ML researcher, and competitive programmer from IIT Indore.

2025 โ€“ Present
M.Tech in Electronics & Signal Processing
IIT Indore ยท Roll No. 2502102014 ยท CGPA 8.8/10
Specializing in digital systems, VLSI design, and AI-driven communications. Thesis on LLM-driven network slicing using O-RAN RIC. Coursework includes Advanced DSP, VLSI Design, Wireless Communications, and Machine Learning.
2021 โ€“ 2025
B.Tech in Electrical & Electronics Engineering
NIT Andhra Pradesh ยท CGPA 8.32/10
Strong foundation in electronics, communication systems, and programming. Active in AI and Robotics Club. Participated in Smart India Hackathon and multiple tech fests.
2025
GATE โ€” Electronics & Communication Engineering
All India Rank: 1297
Qualified GATE ECE with a competitive all-India rank, securing admission to IIT Indore's M.Tech program.
โšก

CPU Architecture

Pipeline design, instruction set architectures, microarchitecture optimization, and hardware performance analysis. Implemented a full RISC-V pipelined processor.

๐Ÿ”ฌ

VLSI Design

RTL design, digital synthesis, timing analysis, and verification. Proficient in Verilog/SystemVerilog with formal verification tools.

๐Ÿ“ก

Signal Processing

DSP algorithms, OFDM, MIMO systems, and physical layer design for 5G NR. Experienced with MATLAB simulation and GNU Radio.

๐Ÿค–

AI / Machine Learning

Deep learning, reinforcement learning, LLMs, and their application to wireless communications and hardware optimization.