Work

Projects

Hardware design, AI research, wireless systems — end-to-end.

Computer Architecture & Hardware

⭐ Featured · Computer Architecture

RISC-V Pipelined Processor Implementation

A complete 5-stage pipelined processor implementing the RV32I ISA in Verilog. Features full hazard detection (data and control hazards), a forwarding/bypassing unit for performance, branch prediction, and complete testbench verification. The design follows classical pipeline architecture: Instruction Fetch → Decode → Execute → Memory → Write-back.

Verilog HDL RISC-V RV32I ISA 5-Stage Pipeline Hazard Detection Unit Data Forwarding Branch Prediction Icarus Verilog

View on GitHub

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Wireless & Networking (AI/ML)

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LLM-Driven Network Slicing via RIC

M.Tech Thesis · IIT Indore · Ongoing

Designing an intelligent network slicing framework using Large Language Models (LLMs) on the O-RAN RAN Intelligent Controller (RIC). The system deploys xApps and rApps to autonomously manage radio resource allocation, QoS enforcement, and slice lifecycle in 5G NR networks. Integrates real-time telemetry with LLM inference for adaptive decision-making.

O-RAN RIC xApp / rApp 5G NR LLM Python Network Slicing

GitHub

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Zero-Day Attack Detection

IEEE Publication · Security ML

ML-based network intrusion detection system for identifying zero-day cyberattacks in real-time network traffic. Uses ensemble classifiers and unsupervised anomaly detection to flag novel attack patterns without prior signatures. Published in IEEE proceedings.

IEEE Published Ensemble ML Anomaly Detection Python Network Security

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AI & Machine Learning

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Automatic Speech Recognition (ASR)

Deep Learning · RNN / LSTM

End-to-end ASR pipeline using deep Bidirectional LSTM networks with CTC loss. Integrated beam search decoding, temporal smoothing, and MFCC feature extraction achieving state-of-the-art Word Error Rate on benchmark corpora.

Bi-LSTM CTC Loss PyTorch MFCC Beam Search

GitHub →

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Neural Modeling of Genetic Circuits

IIT Kanpur Research Internship

Collaborated with Prof. Abhilash Patel at IIT Kanpur to model synthetic genetic circuits using first and second-order system approximations. Employed neural ODEs and RL-based control to simulate biological switches and logic gates, accelerating biological circuit design.

Neural ODEs RL Control Synthetic Biology Python

Research →

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ODIR-5K Eye Disease Classifier

Medical Imaging · Self-Supervised Learning

Tackled long-tail multilabel retinal disease classification using self-supervised ResNet variants with contrastive pretraining. Incorporated focal loss and class-balanced sampling to achieve significant macro F1-score improvements over supervised baselines.

Self-Supervised ResNet Contrastive Loss Medical Imaging PyTorch

GitHub →

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SHL Assessment Recommender

LLM + Vector Retrieval · Production

Semantic retrieval system using Gemini LLM embeddings and a vector database to recommend SHL psychometric assessment modules based on job descriptions. Optimized for sub-100ms inference latency and deployed on Vercel with modular FastAPI backend.

Gemini LLM Vector DB FastAPI Vercel RAG

GitHub →

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Car Repair Shop Management System

Full-Stack · Node.js + MongoDB

Full-stack web application for managing automotive repair shop operations including employee records, service tickets, appointment scheduling, and role-based authentication. Built with Node.js, Express, MongoDB and real-time analytics dashboard.

Node.js Express MongoDB REST API JWT Auth

GitHub →